1. Field of the Invention
The present invention relates to global memory mapping schemes and, more particularly, to a system and method for determining to which of two input/output (I/O) channels an address is mapped.
2. Description of Related Art
The memory requirements of a typical microprocessor system frequently cannot be met with a single memory device. Several memory devices must then be interconnected to form a memory system. In a memory system, capacity is expanded by increasing the number of words and/or by increasing the word length above that attainable from a single memory device. Word length is increased by placing the outputs of two or more memory devices in parallel. The number of words in a memory system is increased by multiplexing outputs from two or more memory devices. Memory devices have features that facilitate this. For example, chip select or chip enable inputs are provided on individual memory devices for this purpose.
A memory system with an increased number of words requires address expansion, that is, it requires expanding the number of memory address bits to which the memory system responds. The number of address bits that a microprocessor provides dictates its memory address space or the range of memory locations it can directly address. Depending upon the size of the memory system, external address decoding logic, in addition to the memory's chip select inputs, may also be required for address expansion.
Random access memory (RAM) is the main memory of a typical computer. As programs are run, they first load into RAM from the disk drive, and the operating system then jumps to the beginning of the program to begin executing it. Program data also loads into the computer's RAM. As changes are made in the data, the contents of the RAM are altered, and when the user finishes with the application, the revised data is copied back to the disk drive.
Read only memory (ROM) is the part of memory where, normally, the basic input/output system (BIOS) of the computer resides. The BIOS is the interface between the computer hardware and the operating system and applications software. Under normal circtnnstances, one cannot write to ROM.
The size of the RAM and ROM, and the locations of various components, is shown with a memory map. A memory map is a graphic representation of the memory locations. FIG. 1 shows a memory map of a typical extended industry standard architecture (EISA) computer system. The remainder of the system's memory map is dependent on the particular requirements of the individual manufacturers.
I/O is a mapped area similar to the memory map. Different addresses, or groups of addresses, are assigned to specific functions. The I/O map is much more extensive and complex, however, with different functions assigned to each of the addresses through FFFFh (65,536 addresses). FIG. 2 shows an EISA computer system I/O map summary.
It is important that computer systems have a single, "cohesive" memory map. Each location must have its own unique address, and memory devices that "own" a particular region must "know" it and, conversely, memory devices that do not "own" a particular region must "know" that also. Heretofore, cohesive systems have been made wherein memory devices have a number of (e.g., eight) "descriptors", that is, a mechanism within the device itself to define its relationships with a memory region. Heretofore, such relationships have been defined with descriptors which map in a positive, identifying manner specific address ranges for specific purposes.
Although the present invention is most directly concerned with memory mapping, it arose because of efforts undertaken to increase I/O throughput within computer systems. Thus some discussion of that topic is appropriately undertaken here.
Considerable effort has been expended heretofore by those skilled in the computer systems development art to increase input/output (I/O) throughput. One approach taken, which approach is discussed in detail in the related applications referenced above, is to specially connect more than one I/O channel [e.g., an Extended Industry Standard Architecture (EISA) channel] to a system bus. This approach has certain limitations, however. For example, in the case of EISA channels, because of their architecture, multiple channels cannot be entirely symmetric. This imposes a number of restraints. First, there is a maximum of fourteen EISA slots available if two channels are used. Second, there must be a specific default EISA bus. All accesses which are not known to go to another channel or to main memory go to the default channel. Third, all Industry Standard Architecture (ISA) adapter cards must go in the default channel. Fourth, EISA channel-to-channel operations which transfer to other channels are not supported, as this introduces a deadlock situation which cannot be handled.
Notwithstanding the restraints mentioned above and, again, as discussed in the related applications, computer systems including system busses capable of supporting more than one I/O channel have been designed. One such system, designed by the assignee of the present invention, is a common interconnect for up to six system nodes: masters, slaves, or both.
Needless to say, a system such as that designed by the assignee of the present invention, including a bus with up to six system nodes and two I/O channels, has complex global memory mapping requirements.
These complex requirements, in turn, cause problems to arise. One problem is that a multitude of descriptors become required to describe the region owned by even a single memory device. Errors arise because of the large number of descriptors that must be employed. A second, related, problem is that use of a large number of descriptors entails use of "deeper" logic, which is slower than less complex logic, because it inherently has more gate delays. A third problem is that the first and second problems mentioned above have heretofore been inevitable, because while those skilled in the art have focused on more artfully using current descriptors, there have been no known pioneering efforts to devise new types of descriptors that simplify memory mapping.